1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a non-volatile memory cell having a floating gate upper surface on which a chemical mechanical polish ("CMP") is applied to enhance device performance.
2. Description of the Relevant Art
There are many types of non-volatile memory known as read only memory (ROM) or programmable read only memory (PROM). Non-volatile memory can be formed in either bipolar or MOS technology. There are various types of MOS PROMs, including, e.g., erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory EPROM (FLASH EPROM).
Non-volatile MOS PROMs can be fabricated using many well-known technologies such as: (i) floating gate tunnel oxide (FLOTOX), (ii) textured polysilicon, (iii) metal nitride oxide silicon (MNOS), and (iv) EPROM-tunnel oxide (ETOX). Program and erase of the corresponding EPROM cell differs depending upon which technology is used. For example, a floating gate tunnel oxide EPROM transistor is programmed (moving electrons into the floating gate) by biasing the control gate, while erasure (moving electrons out of the floating gate) is achieved by biasing the drain. Programming a textured poly-type EPROM device involves electrons tunneling from a first polysilicon to a second polysilicon, wherein erase involves electrons tunneling from the second polysilicon to a third polysilicon. In MNOS-type devices, the charge is stored in discrete traps in the bulk of the nitride. It is generally recognized that stacked polysilicon conductors are used to perform the program and erase function for each form of EPROM.
FIG. 1 illustrates a FLOTOX EEPROM memory cell according to conventional design. The FLOXTOX cell includes a relatively thin tunnel oxide 12 interposed between a doped polysilicon floating gate 14 and a semiconductor topography 10. Tunnel oxide 12 is typically thermally grown upon topography 10 to a thickness of less than e.g., 100 .ANG.. The FLOXTOX cell further includes an interpoly dielectric 16 arranged upon floating gate 14 and underlying a doped polysilicon control gate 18. Fabrication of the FLOXTOX cell may involve forming these layers upon each other above semiconductor substrate 10 and then etching away portions of the layers not masked by a patterned photoresist layer to form the stacked structure shown in FIG. 1. A heavily concentrated dopant distribution which is self-aligned to the opposed sidewalls of the stacked structure may then be forwarded into substrate 10 to form source and drain regions 20 and 22, respectively. A thermally grown oxide layer 24 may be thermally grown upon the periphery of the stacked structure and upon exposed regions of substrate 10. Due to thermal exposure during this process, the impurities within source and drain regions 20 and 22 undergo lateral migration toward the channel region underneath tunnel oxide 12, resulting in the configuration depicted in FIG. 1.
Control gate 18 can be coupled to a word line, and bit line conductors can be formed within contact windows of a dielectric for making contact to drain region 22 (not shown). Charging of floating gate 14 to program the cell can be achieved by grounding source and drain regions 20 and 22 and applying a relatively high voltage to control gate 18. In the programming state, electrons pass through tunnel oxide 12 to floating gate 14 by a tunneling mechanism known as Fowler-Nordheim tunneling. As more electrons accumulate in floating gate 14, the electric field is reduced such that charge becomes stored in the floating gate. Discharge of floating gate 14 to erase the cell can be achieved by grounding control gate 18, floating gate 14, and source region 20 and applying a relatively high voltage to drain region 22.
Because of the increased desire to build faster operating integrated circuits, it has become necessary to increase capacitive coupling between the floating gate and the control gate of the memory cell while simultaneously inhibiting electrons from escaping from the floating gate to the control gate. The control gate-to-floating gate capacitance is dependent upon the thickness of the interpoly oxide arranged between the two gates and the relative permittivity of the interpoly oxide. Unfortunately, the relative permittivity, or dielectric constant, K, of the interpoly oxide limits the amount of gate-to-substrate capacitance that can be achieved when a transistor is in operation. Permittivity, .epsilon., of a material reflects the ability of the material to be polarized by an electric field. The capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, .epsilon..sub.0. Hence, the relative permittivity or dielectric constant of a material is defined as: EQU K=.epsilon./.epsilon..sub.0
Since oxide (i.e., silicon dioxide) has a relatively low K of approximately 3.7 to 3.8, the amount of capacitive coupling between the control gate and the floating gate is somewhat limited.
As mentioned above, the control gate-to-floating gate capacitance is also affected by the thickness of the interpoly oxide. Conventional memory cells typically include a relatively thin interpoly oxide to reduce capacitive coupling between the two gates. Consequently, the voltage (i.e., voltage applied to the control gate) required to initiate electron flow between the drain region and the floating gate is decreased. Unfortunately, the thin interpoly oxide may break down when subjected to an electric field, permitting electrons to pass through the oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the floating gate and the control gate, resulting in data not being properly retained by the memory cell.
Breakdown of the interpoly oxide is particularly a problem if it is thermally grown upon a polysilicon floating gate. Because formation of the floating gate involves deposition of amorphous polysilicon, it is believed that the collimated nature of the floating gate contains an irregular grain structure having various crystal orientations. As a result, surface asperity appears at the interface between the interpoly oxide and the underlying floating gate. It is believed that the irregularity of the polysilicon grain structure prevents strong bonding between silicon atoms of the floating gate and oxygen atoms from the ambient. Since a relatively low temperature of about 800.degree. C. is used to form the interpoly oxide, oxygen atoms cannot easily migrate through localized barriers present in the irregular grain structure to bond with underlying silicon atoms. In other words, there are not enough opportune bond sites proximate the floating gate surface. Using high temperature thermal oxidation is not a viable option because problems, such as impurities moving to undesirable locations (e.g., from the floating gate to the tunnel oxide) may occur via principles of segregation and diffusion. It is postulated that the resulting interpoly oxide is not of high quality. The interface between the interpoly oxide and the floating gate may contain migration pathways through which electrons can pass. Thus, the resulting interpoly oxide formed in the above manner may have an undesirably low breakdown across the interpoly oxide.
It would therefore be desirable to develop a technique for fabricating a memory cell having reduced control gate-to-floating gate capacitance which is substantially resistant to interpoly dielectric breakdown. Fabrication of a relatively thin interpoly oxide between the floating gate and control gate must be avoided. It would be beneficial if the floating gate and interpoly dielectric could be formed such that surface asperity is reduced at the floating gate/interpoly dielectric interface. The resulting memory cell could be transformed quickly into its programming state for immediate data storage. Further, formation of a tunneling current between the floating gate and the control gate of the memory cell would be less likely. Proper data retainage would thus be possible, resulting in a more reliable memory cell.